1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory cell utilizing channel resistance modulation in a semiconductor layer occurring due to remanent polarization of a ferroelectric material, and also relates to a semiconductor memory array using the nonvolatile semiconductor memory cell.
2. Description of the Related Art
Nonvolatile memories using ferroelectric materials are broadly divided into two types: a capacitor-type and a field effect transistor (FET)-type having a gate insulating film made of a ferroelectric film.
The capacitor-type nonvolatile ferroelectric memories, which are similar in structure to dynamic random access memories (DRAMs), hold charges in a ferroelectric capacitor therein and identify whether binary data is 0 or 1 according to the direction of polarization of the ferroelectric material. The polarization accumulated in the ferroelectric capacitor is coupled to charges induced by the upper and lower electrodes thereof and does not dissipate when the voltage is cut off. However, when the binary data is read, the stored polarization is destroyed and the binary data is lost. In this type, therefore, an operation for rewriting the binary data is needed. As a result, the rewriting operation performed in each read operation causes polarization reversal to be repeated so that polarization fatigue presents a problem. In addition, in this structure, since polarization charges are read by a sense amplifier, charges (typically 100 fC) equal to or higher than the sensing limit of the sense amplifier is necessary. The polarization charges per unit area of a ferroelectric material are intrinsic to the material. Hence, even in a miniaturized memory cell, an electrode area of a given size is needed as long as the same material is used. It is therefore difficult to reduce the capacitor size in direct proportion to the miniaturization of process rules, and the capacitor-type ferroelectric memories are thus unsuitable for an increase in capacity.
In contrast, from the FET-type ferroelectric memories, binary data is read by detecting the conductive state of the channel which changes in accordance with the direction of polarization of the ferroelectric film. This allows non-destructive reading of the binary data as well as an increase in the amplitude of an output voltage through the amplifying operation of the FET. As a result, the FET-type ferroelectric memories can be miniaturized in accordance with the scaling law. There has conventionally been proposed a FET-type transistor in which a ferroelectric film, serving as a gate insulating film, is formed on a silicon substrate serving as the channel. Such a structure is called a Metal-Ferroelectric-Semiconductor (MFS) FET.
In a memory cell array in which FET-type ferroelectric memories are arranged in a matrix with rows and columns, binary data is written into a ferroelectric memory by applying a voltage pulse between a gate electrode connected to a word line of the selected memory cell and a source electrode connected to a source line of the selected memory cell. However, when the voltage pulse is applied, the voltage is also applied to other memory cells which are connected to the word line and the source line of the selected memory cell and which are not to be accessed, resulting in error writing of the data, which is so-called “write disturbance”. Thus, typically, a selection switch composed of a MISFET (Metal-Insulator-semiconductor FET), for example, is inserted between the word line and the gate electrode and/or between the source line and the source electrode, thereby preventing such an write disturbance. (see Japanese Laid-Open Publication No. 5-205487, for example)